This invention relates generally to multiplier circuitry. In particular, this invention relates to a multiplier design that uses hard and soft logic in a programmable logic device in order to reduce the dedicated die area required for the multiplier. This design reduces the amount of dedicated die without using the soft logic inefficiently or producing a significant decrease in the performance of the multiplier.
Programmable logic devices (PLDs) include generalized logic circuitry such as look-up tables (LUTs) and sum-of-product based logic that are designed to allow a user to customize the circuitry to the user's particular needs. This configurable logic is typically divided into individual logic circuits that are referred to as logic elements (LEs). As an example, each LE in a PLD may be configured as a 4-input LUT. The LEs may be grouped together to form larger logic blocks referred to as logic array blocks (LABs) that may be configured to share the same resources (e.g., registers and memory). In addition to this configurable logic, PLDs also include programmable interconnect or routing circuitry that is used to connect the inputs and outputs of the LEs and LABs. The combination of this programmable logic and routing circuitry is referred to as soft logic.
Besides soft logic, PLDs may also include hard logic circuitry that implements specific predefined logic functions and thus cannot be configured by the user. One common type of functional circuitry that is implemented in hard logic in PLDs is a multiplier. Multipliers are intensively used in applications such as digital signal processing (DSP), for example. Currently, multipliers that are implemented using hard logic are implemented virtually exclusively in hard logic. Although soft logic may be used to combine several hard multipliers together to form a larger multiplier, none of the existing multiplier implementations divide the multiplier components (e.g., adder stages) that are responsible for performing the multiplication operation into portions that are implemented in hard logic and portions that are implemented in soft logic. The problem with providing multipliers and other types of hard logic circuitry on devices such as PLDs is that it increases the cost of the devices because of the of dedicated die area that is required to implement such circuitry. On the other hand, multipliers that are designed purely in soft logic often make inefficient use of the logic and routing resources and perform slower than equivalent hard logic multipliers. For example, the use of soft logic to perform partial product generation usually requires an excessive amount of LUTs and interconnect resources. For other common multiplier functions such as carry-save addition, the LUTs used for this function are not fully used and thus waste logic and routing. If an adder tree is used as an alternative to carry save addition, then fitting the design to the soft logic architecture can become an issue.
Thus, it would be desirable to create a multiplier design, in a device such as a PLD that uses includes hard and soft logic, that reduces the amount of dedicated die area required for the multiplier. It would be further desirable to design a multiplier using hard and soft logic that reduces the amount of required hard logic without inefficiently using the soft logic. It would be still further desirable to design a multiplier using hard and soft logic that reduces the amount of required hard logic without a significant decrease in the performance of the multiplier.